Submitting Campus
Daytona Beach
Department
Electrical Engineering and Computer Science
Document Type
Patent
Publication/Presentation Date
4-30-2019
Abstract/Description
A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths ( e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/0) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multiplier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations from a general-purpose processor.
Patent Number
US 10,275,219 B2
Assignee
Embry-Riddle Aeronautical University
Application Number
15/807,147
Date Filed
11-8-2017
Scholarly Commons Citation
Almagambetov, A., & Ross, H. R. (2019). Bit-Serial Multiplier for FPGA Applications. , (). Retrieved from https://commons.erau.edu/publication/2215
